1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and a semiconductor structure thereof for improving short channel effect and drain induced barrier lowering, and more particularly, to a method of manufacturing MOS transistors, and a MOS structure thereof that improves short channel effect and drain induced barrier lowering.
2. Description of the Prior Art
For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to the very deep sub micron era such as 65-nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue.
To attain higher performance of a semiconductor device, attempts have been made to use a strained silicon (Si) layer for increasing the mobility of electrons or holes. For example, taking advantage of the lattice constant of SiGe layer being different from that of Si, a strain occurs in the silicon layer growing on the SiGe layer. Since SiGe has a larger lattice constant than Si, the band structure of Si is altered, thereby increasing the mobility of the carriers.
Other attempts have been made to use germanium embedded in a predetermined source/drain region formed by selective epitaxial growth as a compressive strained silicon film to enhance electron mobility in a PMOS transistor, after a gate is formed. An SiGe layer deposited into the predetermined source/drain region often increases the mobility of electron holes of PMOS, but will simultaneously decrease the electron mobility of an NMOS and reduce the efficiency of the transistor. Therefore, during SiGe layer formation, NMOS is usually covered by a silicon nitride layer serving as a mask. After the SiGe layer is formed, the silicon nitride layer will be removed by hot phosphoric acid. However, the surface of the substrate where the predetermined source/drain region of NMOS is disposed will be corroded by hot phosphoric acid. The interface between the gate dielectric layer and the substrate is taken as a reference. The baseline of corroded substrate becomes lower than the aforesaid interface. Therefore, after the implantation process to form a source/drain region, the p/n junction will become deeper than a predetermined depth. As a result, short channel effect and drain induced barrier lowering (DIBL) effect will occur.
Therefore, there is still a need for a MOS transistor device and a method of manufacturing the same to improve problems mentioned above.